좀 더 공부해보려고 해봤습니다.

DUT

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
    Port ( X0, X1, X2, X3 : in std_logic;
        SEL : in std_logic_vector(1 downto 0);
        Y   : out std_logic );
end mux;

architecture Behavioral of mux is

begin
    process(SEL, X0, X1, X2, X3)
    begin
        if SEL = "00" then
            Y <= X0;
        elsif SEL = "01" then
            Y <= X1;
        elsif SEL = "10" then
            Y <= X2;
        elsif SEL = "11" then
            Y <= X3;
        end if;
        
    end process;
end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_mux is
end tb_mux;

architecture Behavioral of tb_mux is
    signal X0, X1, X2, X3 : std_logic;
    signal S : std_logic_vector (1 downto 0);
    signal Y : std_logic;

begin
UUT : entity work.mux port map(
X0 => X0, X1 => x1, X2 => x2, X3 => x3, sel => s, Y => y);

process
    begin
    X0 <= '0';
    x1 <= '1';
    x2 <= '0';
    x3 <= '1';
    
    S <= "00";
    wait for 10ns;
    
    S <= "01";
    wait for 10ns;

    S <= "10";
    wait for 10ns;

    S <= "11";
    wait for 10ns;
    
    report "종료" severity failure;
end process;

end Behavioral;

테스트를 해보고 싶어서 이것저것 다르게 해봤습니다. 대소문자 달라도 되고, 무조건 indirect mapping이라 좀 더 편한 것 같습니다.

waveform

잘 나옵니다